`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:50:49 12/01/2020 
// Design Name: 
// Module Name:    IF_ID 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module IF_ID(
    input clk,
    input reset,
	 input froze,
    input [31:0] instructionIn,
	 input [31:0] PCIn,
    output reg[31:0] instructionOut,
	 output reg[31:0] PCOut
    );
	 
	always @(posedge clk)
	begin
		if(reset)begin
			instructionOut <= 0;
			PCOut <= 0;
		end
		else if(~froze) begin
			instructionOut <= instructionIn;
			PCOut <= PCIn;
		end
		else begin
			instructionOut <= instructionOut;
			PCOut <= PCOut;
		end
	end

endmodule
